Embedded reconfigurable architectures are currently attracting increasing attention in the wireless communications\r\nindustry due to the escalating number of wireless standards in todayâ��s market. Application specific instruction-set\r\nprocessors (ASIPs) present a reconfigurable solution that offers a compromise between programmability and low\r\npower consumption. In this article, the design and implementation of an embedded synchronization and\r\nacquisition ASIP for OFDM based systems is proposed. The engine architecture is presented and the programming\r\nmodel is explained in details. The proposed engine is scalable and it can be configured to support a multitude of\r\nsynchronization algorithms and OFDM standards. While applicable to many OFDM systems, the proposed\r\narchitecture was successfully verified on long term evolution (LTE Rel. 8) and WiMAX 802.16e systems. A partial list\r\nof synchronization and acquisition algorithms are tested on the engine for the two standards, and the results\r\nhighlight the capabilities of the engine. The processor has been synthesized with 0.18�µm standard cell CMOS\r\nlibrary. It is estimated to occupy 1.1 mm2 and the projected power consumption is 7.9mW at 120 MHz, which\r\nmeets the speed requirements of the tested standards. More results are included within the article.
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